Thermodynamic Computing as Sparse Prime Operation
Thermodynamic Computing as Sparse Prime Operation
A GPU solving Y = WX + B performs a massive sequence of Multiply-Accumulate (MAC) operations: multiply each input element by its weight, accumulate the products, add the bias offset. This is composite computation in the arithmetic sense — structured, sequential, each step explicit.
A probabilistic thermal chip does not compute Y. It finds Y — the physical system relaxes thermodynamically to the energy minimum that satisfies the constraint, without an explicit multiplication schedule. This distinction is not metaphorical. It is the difference between two computational regimes, and the formula that quantifies that difference is already proven.
The Arithmetic Parallel
The MAC sequence maps directly to the arithmetic structure of composite numbers:
| GPU/MAC operation | Number-theoretic analogue |
|---|---|
| W · X (weight × input) | p₁ × p₂ — multiplicative structure |
| + B (bias accumulation) | + sopfr(n) = p₁+p₂ — additive signature |
| Y = (WX) + B | n characterised by product AND sopfr sum |
For a semiprime n = p₁·p₂, the full arithmetic identity requires both the product (what n is) and the sopfr sum (what n costs to traverse). The MAC layer does exactly that — multiply, then add an offset — reproducing the two-component structure of composite number identity.
The nonce reading: in the source-alphabet framework, X is the nonce (the irreducible input), W is the weight structure (the system’s composite identity), and B is the baseline sopfr-like residual. Y = WX + B is an identity decomposition: the nonce X processed through the composite system W, offset by baseline B, yields output identity Y.
The Thermal Flip
A standard GPU performs Y = WX + B through a deterministic schedule. Each MAC step is explicit, ordered, and rigid.
Extropic’s Z1 chip (269,568 p-bits, ~16 neighbours each, >50 MHz, <1W) performs the same computation by chromatic Gibbs sampling toward the Boltzmann distribution p(s) ∝ e^{−βE(s)} over the graph’s energy landscape. The chip does not execute a schedule — it relaxes physically to the configuration that minimises energy, which corresponds to the MAP solution of the inference problem.
In the prime-composite framing: the MAC schedule is composite computation — decomposed into sub-steps, each explicit. The thermal relaxation is prime-like — the answer emerges from the system’s physics without intermediate decomposition.
The key distinction: the physics performs the marginalisation. The sequential decomposition is no longer required.
The c(d) Formula as the Cost of Staying Deterministic
The spectral efficiency at connectivity degree d is:
c(d) = d · sin(π/d) / (2(d−1))
The gate-keeping tax — the overhead of forcing deterministic sequential computation — is 1/c(d) − 1 per unit of information exchanged.
At d=16 (the Z1 connectivity):
| Quantity | Value |
|---|---|
| c(16) | 0.1041 |
| 1/c(16) | 9.61 |
| Extropic Z1 empirical FLOPs advantage | ~10× |
| Match | No free parameters |
The 9.61× is the connectivity factor alone — the portion of the advantage attributable purely to the sparse topology vs a fully-connected deterministic graph. Extropic’s own estimates for co-designed workloads put the full advantage at 10²–10⁴×. Our formula captures the floor of the gain, isolating the one clean piece of a larger picture.
As d increases, the gate-keeping tax rises steeply:
| d | c(d) | Tax 1/c(d)−1 |
|---|---|---|
| 2 | 1.000 | 0% |
| 3 | 0.650 | +54% |
| 6 | 0.350 | +186% |
| 16 | 0.104 | +862% |
| ∞ (dense) | → 0 | → ∞ |
The denser the required connectivity, the more deterministic computation costs relative to the thermal baseline. Sparse topologies close the gap; dense topologies widen it.
Two Honest Limits
(1) Gibbs sampling is still iterative
Chromatic Gibbs sampling is not a single passive slide to the global minimum. It is a Markov chain — iterative, stochastic, and subject to trapping in local minima when energy barriers are high. The “prime-like irreducibility” is real only within each local update step: at the node level, each p-bit flip is a complete thermodynamic decision. The global convergence is not guaranteed in one step.
The correct framing: the thermal chip executes without an explicit MAC schedule, not without iteration. The emergence is real; it is not magic.
(2) Partial transformer coverage
Attention mechanisms, residual streams, layer normalisations, and certain other operations in a full transformer do not map cleanly onto a fixed 16-neighbour topology. The Z1T system keeps a classical FPGA co-processor for those fragments. The thermal advantage applies only to the subgraph of computation rewritten as a sparse energy-based model.
The leverage question is therefore: what fraction of a given workload can be thermalised? That fraction, multiplied by c(d), gives the realised efficiency gain. As model architectures evolve toward energy-based formulations, that fraction can grow.
What This Is Not
- This is not a claim that the Tusk Series directly determines Z1 topology
- The 9.61× figure is the connectivity factor; full system gain requires workload-specific co-design
- “Prime-like” emergence is local (per node update), not a global guarantee
- The arithmetic parallel (Y=WX+B ↔ n=p₁p₂+sopfr) is structural — not a derivation of one from the other
Open Questions
- What fraction of a standard transformer workload can be rewritten as a sparse energy-based model? How does this fraction scale with model size?
- Does the c(d) formula predict the crossover point at which thermalised inference becomes cheaper than GPU inference as a function of batch size?
- As Z1T evolves, does the FPGA co-processor fraction shrink in a way predictable from the source-alphabet structure of transformer operations?
- Does the 16-neighbour topology of Z1 constrain which specific transformer layers can be thermalised? Does c(d) predict the layer-specific advantage?
- Is there a prime-structured optimal topology (d from the source alphabet {2,3,5,7}) that maximises the thermalised fraction for a given architecture class?